1. Technical Field
The disclosure relates generally to semiconductor wafer fabrication, and more particularly, to a method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer to have a substantially uniform thickness across the wafer.
2. Background Art
Complementary metal-oxide semiconductor (CMOS) devices built on an extremely thin semiconductor-on-insulator (SOI) substrate have been one of the viable options for continued scaling of CMOS technology to the 22 nm node and beyond. Device characteristics such as threshold voltage (Vt) of an ETSOI device are mainly determined by the thickness of ETSOI. Consequently, SOI thickness variation within a wafer strongly contributes to Vt variation. For the 22 nm node and beyond, the SOI thickness requirement may be about 10 nm or thinner. Currently, SOI wafers are generated having thicknesses that are significantly thicker than 60 nm, and are then thinned to the ETSOI level. One current wafer thinning technique includes oxidizing the bonded or SIMOX (i.e., separated by implantation of oxygen) SOI in a furnace and wet etching the oxide. This approach transfers the within-wafer variation of the initial SOI thickness to the ETSOI. Unfortunately, the resulting thickness variation remains too large for the desired 22 nm devices. In one example, the thickness variation may range +/−20 angstroms (Å) for an initially 700 Å SOI wafer. Other approaches that use ion beam etching to thin the SOI layer result in too extensively damaged wafers to be practicable.